1. Field of the Invention
The present invention relates to a packet data transmitting apparatus and a method therefor, in which packet data consisting of packets are transmitted to the destination by using a hardware router.
2. Description of the Prior Art
Insofar as methods of transmitting data are concerned, there are a line exchange method and a packet transmitting method.
The line exchange method is mostly used, for example, in the electronic switching method. In this method, communication lines are installed, so that the data would not be delayed but would be transmitted with real time.
However, in the line exchange method, the line is occupied for transmitting the data, and therefore, it happens that the lines cannot be effectively used. Further, the communication expense shows severe differences depending on the magnitude of the communication distance. Further, the communication becomes impossible if the other end has a different communication speed.
On the other hand, the packet method carries out the data transmission by dividing the data into packet units, and is used mostly in systems like the CDMA(code division multiple access) in which control signals and data are exchanged between the communicating parties.
The packet consists of a data unit formed in a predetermined length, and the address of the other communicating party.
In this packet transmitting method, when data are transmitted, a line does not have to be occupied, and therefore, the line can be used effectively. Further, the communication becomes possible even if the other party has a different communication speed.
FIG. 1 illustrates a conventional packet data transmitting apparatus.
As shown in FIG. 1, the conventional packet data transmitting apparatus includes: a serial/parallel converting section 100 for converting the incoming serial data into a parallel data; a central processing unit 101 for temporarily storing the output packet parallel data of the serial/parallel converting section 100, and for detecting an address information so as to convert the logical address into a physical address;
a buffer 102 for storing the output parallel packet data from the central processing unit so as to output them in accordance with the FIFO (first in first out) method; a hardware router 103 for transmitting the output parallel packet data to the relevant destination; and another buffer 104 for storing the packet data transmitted from the hardware router 103 so as to output them in the FIFO method.
In the conventional packet data transmitting apparatus, the serial packet data which are received externally are converted into parallel packet data by the serial/parallel converting section 100. Then, the central processing unit 101 receives the data to store them into the internal memory 101 A in a sequential manner.
The parallel packet data which have been stored in the internal memory 101 A are sequentially read by the central processing unit 101 so as to detect the address information from the packet data. Then the central processing unit 101 converts the logical address to a physical address before outputting it.
The parallel data which have been outputted from the central processing unit 101 are stored in the buffer 102, and are outputted in the FIFO method.
The parallel output data which are outputted from the buffer 102 are inputted into the hardware router 103, and are stored into the buffer 104 of the destination. Then they are outputted in the FIFO method to be transmitted to the destination.
In this conventional packet data transmitting apparatus, the central processing unit reads the destination address of the received data so as to transmit the packet data to the destination.
Therefore, in a system requiring multitasking, an over-load is imposed on the central processing unit, thereby lowering the operating performance. In the case where a large amount of packet data is inputted into the central processing unit, errors are liable to occur due to the over-load on the central processing unit.
Further, the central processing unit tackles one by one in detecting the address information of the packet data, and therefore, the peripheral circuits of the central processing unit becomes complicated.